Optimized Model and Standard Cell Logic Library for Subthreshold Circuit Design
The U.S. Navy seeks to commercialize a method and standard cell logic library for developing circuits that operate in the subthreshold region.
The subthreshold region is a rarely used operating region for Metal Oxide Field Effect Transistor (MOSFET) devices. Generally, circuits operate in the higher voltage region known as the saturation region. Voltage in the subthreshold region is characterized by being below the threshold voltage. This results in much lower power consumption due to a lower applied electric field. Thus, subthreshold circuits are ideal for low power applications such as remote and unattended sensors that favor reduced energy consumption over system performance. Unfortunately, due to the subthreshold region’s limited use, Simulation Program with Integrated Circuit Emphasis (SPICE) models provided by foundries do not properly characterize the region. This results in undependable subthreshold simulations and circuit designs. A proper model is needed for the accurate design of subthreshold circuits.
Scientists and Engineers at SSC Pacific completed fabrication runs that included specific test vehicles needed to characterize the TSMC 0.25 µm process in the subthreshold region. The data collected by measuring the devices was used to optimize the foundry’s SPICE model. SSC Pacific test data shows that the optimized model can properly characterize the process throughout the entire operating range better than the foundry model, especially in the subthreshold region of operation. The optimized model was used to create a subthreshold standard cell library. The library enables the design of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) having a power savings of up to 6 orders of magnitude for some applications.
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- SD 1172, November 2013. SSC Pacific, San Diego, CA 92152–5001. Approved for public release; distribution is unlimited.