Technology Transfer SSC Pacific
Noise-assisted Morphable Logic Gates 

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The U.S. Navy seeks nonexclusive licensees to mature and commercialize reconfigurable and reliable logic gates that operate at an optimum level when noise is present.


As computer components shrink in size and increase in speed, fundamental noise characteristics are encountered that cannot be suppressed or eliminated. Stochastic Resonance (SR) highlights the possibility that noise, a universal phenomena and yet one considered to be a nuisance, may actually play a constructive role in nonlinear circuit design. Influenced by this idea, an SSC Pacific inventor partnered with academia to develop very reliable and reconfigurable logic gates by exploiting nonlinearity in the presence of a noise-floor.

The Technology

When the inventors investigated the response of a nonlinear circuit to input signals (taken to be the sum of two aperiodic rectangular waves), they found that in an optimal band of noise, the output was a logical combination of the input signals. The inventors coined this phenomenon Logical Stochastic Resonance (LSR). LSR allows a logic gate to operate at optimum performance when a certain level of noise is present. Because the noise level needed for optimum performance is comparable to levels needed for the smallest transistors on the market, the logic gates could be used to make existing microchips even smaller. And by adjusting the threshold of the noise-floor, the logic gates can switch or “morph” between logic functions on the fly – from AND to OR, and NAND to NOR – providing the foundation for a reconfigurable computer processor. This technology:

  • Produces stable consistent logic outputs in the presence of a relatively wide band of moderate noise;
  • Uses existing integrated circuit manufacturing processes;
  • Is useful in nanoelectronic devices, synthetic biology scenarios, and other applications;
  • Raises the intriguing possibility that LSR could be used for nontraditional computing systems, even in the quantum realm
  • Provides the basic ingredients for a dynamically reconfigurable circuit.
  • Development Status

  • U.S. patents issued: 7,924,059, 8,436,637; patent pending: 13/380154
  • R&D: $100K over 2 yrs.
  • TRL 3: Experimental critical function and characteristic proof of concept
  • Experimental logic board fabricated from single-crystal silicon using standard e-beam lithography and surface nanomachining
  • Publications:

  • Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor. Physical Review Letters, 13 March 2009.
  • Noisy Logic. Physical Review Focus, 13 March 2009.
  • Realization of reliable and flexible logic gates using noisy nonlinear circuits. Applied Physics Letters, 11 November 2009.
  • A noise-assisted reprogrammable nanomechanical logic gate. NanoLetters, 10 March 2010.
  • Logical stochastic resonance. Chemical Physics, 5 October 2010.
  • Creating morphable logic gates using logical stochastic resonance in an engineered gene network. EPL, 11 January 2011.
  • Noise-aided computation within a synthetic gene network through morphable and robust logic gates. Physical Review E, 11 April 2011.
  • Reprogrammable biological logic gate that exploits noise. 2011 IEEE Biomedical Circuits and Systems Conference.
  • Logical stochastic resonance with correlated internal and external noises in a synthetic biological logic block. Chaos, 29 December 2011.
  • For more information on technology transfer, please contact us at (619) 5535118 or email       
    SD 1155, June 2013. SSC Pacific, San Diego, CA 921525001. Approved for public release; distribution is unlimited.

    SSC Pacific
    Updated: 7/3/2013 1:12 PM EST   Published (1.0)