A new modular sensor suite was built to house the Smart Cameras on the URBOT (Fig 12). The stereo cameras are fixed on a 10cm baseline which is easily accommodated between the URBOT tracks. To maintain the inspection and surveillance capability of the URBOT, a small Sony block camera is mounted between the stereo pair. On the outside of either Smart Camera a halogen head light is mounted. These lights are primarily for tele-operation at night but will also be used to test the feasibility of using stereo vision under vehicle illumination.
Figure 12. The MPRS URBOT.
The sensor housing also holds the Observer CPU, which is responsible for controlling all the hardware in the housing, collecting data from the stereo cameras, processing the data and sending the arc votes to the navigation processor.The Observer CPU is a CM-i686 single-board computer (SBC) from Compulab. The processor is a National Semiconductor Geode clocked at 300MHz and is running a Linux operating system. The Compulab SBC is stacked on top of a breakout board developed at SSC San Diego (Fig. 13). The breakout board (called the 686 daughter board) is used to bring out the connections of the 686 to connectors suitable to use for integration with other systems. The daughter board also adds significant capabilities, including a 1-million-gate FPGA and an 8051 microcontroller with CAN bus and digital to analog outputs. The daughter board can also be used in a standalone mode without the 686 SBC. Combined, the 686 and daughter board provide 10/100 Ethernet, CAN bus, 7 serial ports, 3 host USB ports, an I2C bus, A/D, D/A, over 50 digital I/O lines and more. The daughter board has a footprint of 7.1x11.2cm and together with the 686 SBC requires only about 4W.
Figure 13. SSC San Diego 686 daughter board with Compulab CM-i686 SBC.
The obstacle-avoidance software has been ported from the Matlab simulation to the 686 processor. Using simulated data for the obstacle map, the CPU is able to process the data (including dead reckoning the map) and output the arc votes at a 10-Hz rate using less the 5% of the CPU capacity.